Proceedings of the 37th Annual Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model
Proceedings of the conference on Design, automation and test in Europe
A statistical model for estimating the effect of process variations on crosstalk noise
Proceedings of the 2004 international workshop on System level interconnect prediction
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
BEOL variability and impact on RC extraction
Proceedings of the 42nd annual Design Automation Conference
Statistical modeling of cross-coupling effects in VLSI interconnects
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analytical models for crosstalk excitation and propagation in VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Capacitive coupling noise in high-speed VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. Statistical approaches have been suggested as the most effective substitute for corner-based approaches to deal with the variability of present process technology nodes. This paper introduces a statistical analysis of the crosstalk-aware delay of coupled interconnects considering process variations. The few existing works that have studied this problem suffer not only from shortcomings in their statistical models, but also from inaccurate crosstalk circuit models. We utilize an accurate distributed RC-p model of the interconnections to be able to model process variations close to reality. The considerable effect of correlation among the parameters of neighboring wire segments is also indicated. Statistical properties of the crosstalk-aware output delay are characterized and presented as closed-formed expressions. Monte Carlo Spice-based experimental results demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay when crosstalk is present.