Crosstalk analysis in nanometer technologies
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An accurate analytical crosstalk model for RC interconnect
CISST'08 Proceedings of the 2nd WSEAS International Conference on Circuits, Systems, Signal and Telecommunications
Single Event crosstalk shielding for CMOS logic
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk pulsewidth calculation
Microelectronics Journal
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of on-line clock jitter fault detection circuit for time-error-tolerant system
WSEAS TRANSACTIONS on SYSTEMS
Receiver modeling for static functional crosstalk analysis
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Single event crosstalk prediction in nanometer technologies
Analog Integrated Circuits and Signal Processing
Coupling induced soft error mechanisms in nanoscale CMOS technologies
Analog Integrated Circuits and Signal Processing
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Rapid technology scaling along with the continuous increase in the operation frequency cause the crosstalk noise to become a major source of performance degradation in high-speed integrated circuits. This paper presents an efficient metric to estimate the capacitive crosstalk in nanometer high-speed very large scale integration circuits. In particular, we provide closed-form expressions for the peak amplitude, the pulsewidth, and the time-domain waveform of the crosstalk noise. Experimental results show that the maximum error of our noise predictions is less than 13%, while the average error is only 5.82%.