Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Dynamic Noise Analysis with Capacitive and Inductive Coupling
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Pre-Routing Estimation of Shielding for RLC Signal Integrity
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Controlling Inductive Coupling in Wide Global Signal Busses Through Swizzling
Analog Integrated Circuits and Signal Processing
Effects of coupling capacitance and inductance on delay uncertainty and clock skew
Proceedings of the 44th annual Design Automation Conference
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Reducing signal timing variations in inter-core busses
Integration, the VLSI Journal
Crosstalk modeling for coupled RLC interconnects with application to shield insertion
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient shield insertion for inductive noise reduction in nanometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Capacitive coupling noise in high-speed VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FastCap: a multipole accelerated 3-D capacitance extraction program
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work discusses the Semi-Random Net Reordering (SRNR) technique as a means to improve signal integrity and predictability of timing characteristics for wide routing bundles. The work shows that SRNR is capable of almost 90% reduction in induced noise and noise variation between wires of a routing bundle. The technique is also capable of considerable improvements in worst case propagation delay and delay variations as well as improvements in transition speed and its variations. SRNR has the advantage of close-to-zero cost and applicability even under the strictest of routing methodologies.