Proceedings of the 17th ACM Great Lakes symposium on VLSI
DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Semi-random net reordering for reducing timing variations and improving signal integrity
Microelectronics Journal
Low complexity encoder for crosstalk reduction in RLC modeled interconnects
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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This paper shows that the worst case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses