Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Minimization of Crosstalk Noise, Delay and Power Using a Modi.ed Bus Invert Technique
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Proceedings of the 2006 international symposium on Physical design
Reliable crosstalk-driven interconnect optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Power characteristics of inductive interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FastCap: a multipole accelerated 3-D capacitance extraction program
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As technology scales down to nanometer technology, coupling effects between neighboring wires become very important, and have a significant impact on the power consumption of on-chip interconnects. Especially, on-chip inductive effects need to be taken into account due to low-resistance metal interconnections and faster clock rates in today's SoC design. In this paper, we propose a low power dynamic bus encoding scheme which simultaneously reduces capacitive and inductive effects by the measurement of the real RLC model. Our experimental results show that our approach can save the power consumption of the bus up to 12%.