Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Resource-constrained low-power bus encoding with crosstalk delay elimination
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Proceedings of the 2006 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design
Journal of Systems Architecture: the EUROMICRO Journal
An efficient segmental bus-invert coding method for instruction memory data bus switching reduction
EURASIP Journal on Embedded Systems
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
Microprocessors & Microsystems
Sequence-switch coding for low-power data transmission
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects
Microelectronics Journal
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This paper presents two bus coding schemes for power optimization of application-specific systems: partial pus-invert coding and its extension to multiway partial bus-invert coding. In the first scheme, only a selected subgroup of bus lines is encoded to avoid unnecessary inversion of relatively inactive and/or uncorrelated bus lines which are not included in the subgroup. In the extended scheme, we partition a bus into multiple subbuses by clustering highly correlated bus lines and then encode each subbus independently. We describe a heuristic algorithm of partitioning a bus into subbuses for each encoding scheme. Experimental results for various examples indicate that both encoding schemes are highly efficient for application-specific systems.