Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Narrow bus encoding for low-power DSP systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
An Automated Shielding Algorithm and Tool For Dynamic Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Wire Placement for Crosstalk Energy Minimization in Address Buses
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partitioned bus coding for energy reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Probabilistic crosstalk delay estimation for ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal derivation of optimal active shielding for low-power on-chip buses
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The impact of Miller and coupling effects on single event transient in logical circuits
Microelectronics Journal
Low complexity encoder for crosstalk reduction in RLC modeled interconnects
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Bus encoder design for reduced crosstalk, power and area in coupled VLSI interconnects
Microelectronics Journal
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In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. This paper presents two efficient bus-coding methods. The proposed methods simultaneously reduce more dynamic power dissipation and wire propagation delay than existing bus encoding methods. Our methods also reduce more total power consumption than other encoding methods. Simulation results show that the proposed method I reduces coupling activity by 26.7-38.2% and switching activity by 3.7%-7% on 8-bit to 32-bit data buses, respectively. The proposed method II reduces coupling activity by 27.5-39.1% and switching activity by 5.3-9% on 8-bit to 32-bit data buses, respectively. Both the proposed methods reduce dynamic power by 23.9-35.3% on 8-bit to 32-bit data buses and total propagation delay by up to 30.7-44.6% on 32-bit data buses, and eliminate the Type-4 coupling. Our methods also reduce total power consumption by 23.6-33.9%, 23.9-34.3%, and 24.1-34.6% on 8-bit to 32-bit data buses with the 0.18, 0.13, and 0.09@mm technologies, respectively.