Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep sub-micron (DSM) technologies, the effect of on-chip inductance has increased due to increasing clock frequency, reducing signal rise times and increasing on-chip interconnect length. This issue is a concern for signal integrity and overall chip performance. Therefore, this research work introduces an efficient bus encoder using Bus Inverting (BI) method. This method considerably reduces crosstalk, delay and power dissipation in RLCmodeled circuits. The proposed encoder dissipates lower power which makes it suitable for current high-speed low power VLSI interconnects. It has been observed that on an average, the proposed encoder reduces power dissipation and propagation delay by 67.86% and 46.78%, respectively.