Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

Simultaneous signal and power routing under K model

Proceedings of the 2001 international workshop on System-level interconnect prediction

An efficient analytical model of coupled on-chip RLC interconnects

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

Simultaneous shield insertion and net ordering under explicit RLC noise constraint

Proceedings of the 38th annual Design Automation Conference

Inductance 101: analysis and design issues

Proceedings of the 38th annual Design Automation Conference

Towards global routing with RLC crosstalk constraints

Proceedings of the 39th annual Design Automation Conference

Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses

Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems

A twisted-bundle layout structure for minimizing inductive coupling noise

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

Formulae and applications of interconnect estimation considering shield insertion and net ordering

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Inductance Modeling for On-Chip Interconnects

Analog Integrated Circuits and Signal Processing

Post global routing RLC crosstalk budgeting

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Layout techniques for on-chip interconnect inductance reduction

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

DEPOGIT: dense power-ground interconnect architecture for physical design integrity

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Crosstalk-aware domino logic synthesis

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Shielding area optimization under the solution of interconnect crosstalk

Journal of Computer Science and Technology

A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design

Integration, the VLSI Journal

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

Full-chip multilevel routing for power and signal integrity

Integration, the VLSI Journal

Efficient shield insertion for inductive noise reduction in nanometer technologies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Low complexity encoder for crosstalk reduction in RLC modeled interconnects

VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test