Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect layout optimization under higher-order RLC model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Quick On-Chip Self- and Mutual-Inductance Screen
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
Simultaneous signal and power routing under K model
Proceedings of the 2001 international workshop on System-level interconnect prediction
A decoupling method for analysis of coupled RLC interconnects
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Formulae and applications of interconnect estimation considering shield insertion and net ordering
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Error-correction and crosstalk avoidance in DSM busses
Proceedings of the 2003 international workshop on System-level interconnect prediction
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Error-correction and crosstalk avoidance in DSM busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Shielding area optimization under the solution of interconnect crosstalk
Journal of Computer Science and Technology
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog circuit shielding routing algorithm based on net classification
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient shield insertion for inductive noise reduction in nanometer technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A reliable and power efficient flow-control method to eliminate crosstalk faults in network-on-chips
Microprocessors & Microsystems
Data bus swizzling in TSV-based three-dimensional integrated circuits
Microelectronics Journal
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For multiple coupled RLC nets, we formulate the min-area simultaneous shield insertion and net ordering SINO/NB-&ngr; problem to satisfy the given noise bound. We develop an efficient and conservative model to compute the peak noise, and apply the noise model to a simulated-annealing (SA) based algorithm for the SINO/NB-&ngr; problem. Extensive and accurate experiments show that the SA-based algorithm is efficient, and always achieves solutions satisfying the given noise bound. It uses up to 71\% and 30\% fewer shields when compared to a greedy based shield insertion algorithm and a separated shield insertion and net ordering algorithm, respectively. To the best of our knowledge, it is the first work that presents an in-depth study on the min-area SINO problem under an explicit noise constraint.