Minimum crosstalk channel routing
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Simultaneous shield insertion and net ordering under explicit RLC noise constraint
Proceedings of the 38th annual Design Automation Conference
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
An Introduction to Error Correcting Codes with Applications
An Introduction to Error Correcting Codes with Applications
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Power reduction techniques for microprocessor systems
ACM Computing Surveys (CSUR)
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
Proceedings of the 2006 international workshop on System-level interconnect prediction
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delays and lead to logic faults, particularly when adjacent lines switch with opposite transitions. At the same time system-level interconnects have also become more susceptible to other less predictable forms of interference such as noise induced by power grid fluctuations, electromagnetic interference, and alpha particle radiation. Previous work has treated these systematic and non-systematic forms of noise separately.In this paper we propose to make system level interconnects more robust using encoding that simultaneously addresses error correction requirements and crosstalk noise avoidance. This is more efficient than satisfying these requirements separately. We give algorithms for obtaining optimal encodings, and present a practical class of codes called boundary shift codes. We evaluate the overhead of our method and make comparisons to using error correction with simple shielding.