Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A bus delay reduction technique considering crosstalk
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Error-correction and crosstalk avoidance in DSM busses
Proceedings of the 2003 international workshop on System-level interconnect prediction
Quantifying Error in Dynamic Power Estimation of CMOS Circuits
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Low-power on-chip communication based on transition-aware global signaling (TAGS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect accelerating techniques for sub- 100-nm gigascale systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching sensitive driver circuit to combat dynamic delay in on-chip buses
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling delay and noise in arbitrarily coupled RC trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose a smart repeater that consumes less energy and is suitable for driving global interconnections in nanometre technologies. When there is coupling between interconnects, the effective capacitance of a given wire is a function not only of the physical geometry, but also the relative switching pattern described by the bits on the wire in question (the victim) and the adjacent wires (aggressors). The drive strength of a traditional repeater is static, resulting in a spread of the propagation delay, with the repeater strength being essentially too much for every bit pattern other than the worst-case pattern. In the proposed SMART repeater, the drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. By disconnecting part of the repeater when it is not needed, the total load capacitance to the previous stage is reduced, resulting in reduced energy consumption for those instances. It is shown that the potential average saving in energy can be as much 15% with a 18% jitter reduction over a traditional repeater for typical global wire lengths in nanometre technologies.