Interconnect accelerating techniques for sub- 100-nm gigascale systems

Authors:
Hong-Yi Huang;Shih-Lun Chen
Affiliations:
Very Large Scale Integration/Computer-Aided Design Laboratory, Department of Electronic Engineering, Fu-Jen Catholic University, Taipei 24205, Taiwan, R.O.C.;Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University, Hsinchu 30050, Taiwan, R.O.C.
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Year:
2004

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Abstract

This work describes new circuits called capacitor coupling trigger and capacitor coupling accelerator (CCA) circuits used to reduce the long interconnect RC delay in sub-100-nm processes. The proposed circuits use capacitors to split the output driving paths to eliminate the short-circuit current and thus improve the signal transition time. Besides, the capacitor coupling technique is applied to adjust the gate threshold voltage of the proposed circuits and isolate the input signal from the output driving transistors. The proposed circuits are faster than the prior circuits. Furthermore, the CCA can be applied to bi-directional interface, multiports bus, field-programmable gate array interconnections, and complex dynamic logic circuits.