Interleaving buffer insertion and transistor sizing into a single optimization

Authors:
Yanbin Jiang;Sachin S. Sapatnekar;Cyrus Bamji;Juho Kim
Affiliations:
Iowa State Univ., Ames;Univ. of Minnesota, Minneapolis;Cadence Design Systems, San Jose, CA;Sogang Univ., Seoul, South Korea
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1998

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Abstract

This work presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power delay and area-delay tradeoffs. The purpose of this work is to examine how combining a sizing algorithm with buffer insertion will help us achieve better area delay or power-delay tradeoffs, and to determine where and when to insert buffers in a circuit, The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like gate sizing algorithm alone, as is illustrated by several area delay tradeoff curves shown in this paper.