A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Gate sizing for constrained delay/power/area optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Interleaving buffer insertion and transistor sizing into a single optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Timing-driven placement using design hierarchy guided constraint generation
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Combining Technology Mapping with Post-Placement Resynthesis for Performance Optimization
ICCD '98 Proceedings of the International Conference on Computer Design
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Incremental Placement for Timing Optimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A network-flow approach to timing-driven incremental placement for ASICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
A solution approach to the fixed charge network flow problem using a dynamic slope scaling procedure
Operations Research Letters
BICoB '09 Proceedings of the 1st International Conference on Bioinformatics and Computational Biology
Impact of local interconnects on timing and power in a high performance microprocessor
Proceedings of the 19th international symposium on Physical design
On incremental component implementation selection in system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs
Proceedings of the International Conference on Computer-Aided Design
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay under area constraints by simultaneously considering the benefits and costs of all transforms (as opposed to considering them sequentially after applying each transform). The circuit transforms we employ include, but are not limited to, incremental placement, two types of buffer insertion, cell resizing and cell replication. The problem is modeled as a min-cost network flow problem, in which nodes represent circuit transform options. By carefully determining the structure of the network graph and the cost of each arc, a set of near-optimal transform options can be obtained as those whose corresponding nodes in the network graph have the min-cost flow passing through them. We also tie the transform selection network graph to a detailed placement network graph with TD arc costs for cell movements. This enables our algorithms to incorporate considerations of detailed placement cost for each synthesis transform along with the basic cost of applying the transform in the circuit. We have tested our algorithms on three sets of benchmarks under 3--10% area increase constraints, and obtained up to 48% and an average of 27.8% timing improvement. Our average improvement is relatively 40% better (8.2% better by an absolute measure) than applying the same set of transforms in a good sequential order that is used in many current techniques. Considering only synthesis transforms (no replacement), our technique is relatively 50% better than the sequential approach.