Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 39th annual Design Automation Conference
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
Techniques for effective distributed physical synthesis
Proceedings of the 44th annual Design Automation Conference
The coming of age of physical synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Approximation algorithms for a facility location problem with service capacities
ACM Transactions on Algorithms (TALG)
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The approximation scheme for peak power driven voltage partitioning
Proceedings of the International Conference on Computer-Aided Design
Low-power clock trees for CPUs
Proceedings of the International Conference on Computer-Aided Design
Fast approximation for peak power driven voltage partitioning in almost linear time
Proceedings of the International Conference on Computer-Aided Design
Power-driven global routing for multisupply voltage domains
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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In nanometer technologies, even local interconnects are believed to cause major impact on timing, power, repeaters, and routability in VLSI circuits. Although empirical studies exist, there is little comprehensive work that explores the impact of local interconnects on both timing and power in a real high performance microprocessor design in a quantitative manner. To address the void, this article presents results from the extensive study carried out on RTL-to-layout synthesized (RLS) and semi-manually designed structured data path (SDP) blocks in a 45 nm technology microprocessor core. The study shows that for synthesized blocks local interconnects contribute $1/3rd to the worst internal timing paths, on average; in case of datapath blocks, the same contribution is $1/5th. Moreover, regardless of the design style, the interconnects contribute to more than 30% to the dynamic/glitch power. This points to severity of impact due to local interconnects in today's high performance designs and implies that algorithms/approaches underlying existing synthesis/physical design tools/methodologies have limited success in mitigating the same.