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DAC '93 Proceedings of the 30th international Design Automation Conference
An efficient zero-skew routing algorithm
DAC '94 Proceedings of the 31st annual Design Automation Conference
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Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
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Proceedings of the 2004 international workshop on System level interconnect prediction
Reducing clock skew variability via cross links
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Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
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Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the International Conference on Computer-Aided Design
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Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Clocks are known to be major source of power consumption in digital circuits, especially in high performance microprocessors. With the technology scaling, the increasingly capacitive interconnects contribute to more than 40% of the local clock power. In this paper, we propose a clustering algorithm for them inimization of the power in local clock tree, which is shown to be equivalent to the minimization of interconnect capacitance in the tree. Given a set of sequentials and their locations, clustering is performed to determine the clockbuffers that are required to synchronize the sequentials, where a cluster implies that a clock buffer drives all the sequentials in the cluster. The clustering algorithm uses minimum spanning tree (MST) metric to estimate the interconnect capacitance and ensures the optimality of the solution, when no capacity constraints are applied. The buffers are then sized and clock nets arerouted to minimize the delay, slope, and skew constraints. We compare the clocktrees obtained by our clustering and the competitive approaches on several blocks from a microprocessor design in 65nm technology. The comparison shows that our algorithm improves the clock tree capacitance consistently by up to 21%.