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Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
A clock-tuning circuit for system-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Proceedings of the 2007 international symposium on Physical design
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
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VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
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Proceedings of the 44th annual Design Automation Conference
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Proceedings of the 44th annual Design Automation Conference
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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VLSID '08 Proceedings of the 21st International Conference on VLSI Design
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Proceedings of the Conference on Design, Automation and Test in Europe
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Proceedings of the Conference on Design, Automation and Test in Europe
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Addressing lifetime performance degradation caused by circuit ageing has been a topic of active research for the past few years. In this paper we present a different perspective to this problem, by leveraging the presence of clock tuning elements that are commonly available in high-performance designs. By combining clock tuning elements with on-chip sensors for predicting setup/hold-time violations, we introduce a new clock tuning mechanism that operates on-the-fly and it maintains the maximum achievable performance in-system for each circuit sample affected by ageing.