A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Timing analysis including clock skew
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing analysis with crosstalk is a fixpoint on a complete lattice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Voltage-Aware Static Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speedpath prediction based on learning from a small set of examples
Proceedings of the 45th annual Design Automation Conference
Statistical diagnosis of unmodeled systematic timing effects
Proceedings of the 45th annual Design Automation Conference
A framework for block-based timing sensitivity analysis
Proceedings of the 45th annual Design Automation Conference
Silicon feedback to improve frequency of high-performance microprocessors: an overview
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Path selection for monitoring unexpected systematic timing effects
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Speedpath analysis based on hypothesis pruning and ranking
Proceedings of the 46th Annual Design Automation Conference
PSTA-based branch and bound approach to the silicon speedpath isolation problem
Proceedings of the 2009 International Conference on Computer-Aided Design
A statistical diagnosis approach for analyzing design-silicon timing mismatch
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speedpath analysis under parametric timing models
Proceedings of the 47th Design Automation Conference
ACM SIGDA Newsletter
ACM SIGDA Newsletter
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation
Proceedings of the International Conference on Computer-Aided Design
On the optimality of K longest path generation algorithm under memory constraints
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A sensor-assisted self-authentication framework for hardware trojan detection
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Timing, test, reliability, and noise are modeled and abstracted in our design and verification flows. Specific EDA algorithms are then designed to work with these abstracted models, often in isolation of other effects. However, tighter design margins and higher reliability issues have increased the need for accurate models and algorithms. We propose utilizing silicon data to tune and improve the EDA tools and flows. In this paper we describe a silicon methodology to isolate silicon speedpath environments and feed these into a simulation framework to temporally and spatially isolate specific speedpaths in order to model and understand the real effects. This is done using accurate electrical speedpath modeling techniques which may be used to tune the accuracy and correlation of the design models. The effort required to distinguish the many different electrical effects will be outlined.