Novel optical probing technique for flip chip packaged microprocessors
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On Silicon-Based Speed Path Identification
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Silicon speedpath measurement and feedback into EDA flows
Proceedings of the 44th annual Design Automation Conference
Speedpath prediction based on learning from a small set of examples
Proceedings of the 45th annual Design Automation Conference
A framework for block-based timing sensitivity analysis
Proceedings of the 45th annual Design Automation Conference
Efficient block-based parameterized timing analysis covering all potentially critical paths
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Post-silicon timing characterization by compressed sensing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Speedpath analysis under parametric timing models
Proceedings of the 47th Design Automation Conference
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations
Proceedings of the 47th Design Automation Conference
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The identification of speed-limiting paths, or simply speedpaths, in silicon debug is a crucial step, required for both "fixing" failing paths and for accurate learning from silicon data. We propose using characterized, pre-silicon, variational timing models to identify speedpaths that can best explain the observed delays from silicon measurements. Delays of all logic paths are written as affine functions of process parameters, called hyperplanes, and a branch and bound approach is then applied to find the "best" path combinations. Our method has been tested on a set of ISCAS-89 circuits and the results show that it accurately identifies the speedpaths in most cases, and that this is achieved in a very efficient manner.