First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
A linear-time approach for static timing analysis covering all process corners
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Efficient computation of the worst-delay corner
Proceedings of the conference on Design, automation and test in Europe
Silicon speedpath measurement and feedback into EDA flows
Proceedings of the 44th annual Design Automation Conference
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient block-based parameterized timing analysis covering all potentially critical paths
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Proceedings of the 46th Annual Design Automation Conference
Quantifying robustness metrics in parameterized static timing analysis
Proceedings of the 2009 International Conference on Computer-Aided Design
PSTA-based branch and bound approach to the silicon speedpath isolation problem
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
Speedpath analysis under parametric timing models
Proceedings of the 47th Design Automation Conference
Integration, the VLSI Journal
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Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitivities of the timing slacks to parameter variations. This additional slack information enables designers to examine paths that have large sensitivities to various parameters: such paths are not robust, even though they may have large nominal slacks and may hence be ignored in traditional timing analysis. We present a framework for block-based timing analysis, where the parameters are specified as ranges -- rather than statistical distributions which are hard to know in practice. We show that our approach -- which scales well with the number of processors -- is accurate at all values of the parameters within the specified bounds, and not just at the worst-case corner. This allows the designers to quantify the robustness of the design at any design point. We validate our approach on circuit blocks extracted from a commercial 45nm microprocessor.