Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Explicit computation of performance as a function of process variation
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On path-based learning and its applications in delay test and diagnosis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis using Levelized Covariance Propagation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 2005 international symposium on Physical design
Fast interval-valued statistical interconnect modeling and reduction
Proceedings of the 2005 international symposium on Physical design
Optimization objectives and models of variation for statistical gate sizing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model
Proceedings of the 42nd annual Design Automation Conference
A general framework for accurate statistical timing analysis considering correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
CAD tools for variation tolerance
Proceedings of the 42nd annual Design Automation Conference
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Probabilistic dual-Vth leakage optimization under variability
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
VGTA: Variation Aware Gate Timing Analysis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Variability-Driven Buffer Insertion Considering Correlations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interval-valued reduced order statistical interconnect modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical analysis and optimization in the presence of gate and interconnect delay variations
Proceedings of the 2006 international workshop on System-level interconnect prediction
Statistical crosstalk aggressor alignment aware interconnect delay calculation
Proceedings of the 2006 international workshop on System-level interconnect prediction
Process-induced skew reduction in nominal zero-skew clock trees
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Parameterized block-based non-gaussian statistical gate timing analysis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Statistical Bellman-Ford algorithm with an application to retiming
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An exact algorithm for the statistical shortest path problem
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Robust extraction of spatial correlation
Proceedings of the 2006 international symposium on Physical design
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis
Proceedings of the 2006 international symposium on Physical design
Fast buffer insertion considering process variations
Proceedings of the 2006 international symposium on Physical design
Clock Distribution Architectures: A Comparative Study
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Advances in Computation of the Maximum of a Set of Random Variables
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical Analysis of Capacitance Coupling Effects on Delay and Noise
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Statistical gate delay calculation with crosstalk alignment consideration
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
SACI: statistical static timing analysis of coupled interconnects
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Interval-valued statistical modeling of oxide chemical-mechanical polishing
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical critical path analysis considering correlations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A unified framework for statistical timing analysis with coupling and multiple input switching
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing using incremental parameterized statistical timing analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical gate sizing for timing yield optimization
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Non-gaussian statistical interconnect timing analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Analyzing timing uncertainty in mesh-based clock architectures
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
Refined statistical static timing analysis through
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Statistical logic cell delay analysis using a current-based model
Proceedings of the 43rd annual Design Automation Conference
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
IEEE Design & Test
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Variation-aware routing for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Estimating path delay distribution considering coupling noise
Proceedings of the 17th ACM Great Lakes symposium on VLSI
DFM issues for 65nm and beyond
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the 2007 international workshop on System level interconnect prediction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Practical variation-aware interconnect delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A linear-time approach for static timing analysis covering all process corners
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A framework for statistical timing analysis using non-linear delay and slew models
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new statistical max operation for propagating skewness in statistical timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction
Proceedings of the conference on Design, automation and test in Europe
Use of statistical timing analysis on real designs
Proceedings of the conference on Design, automation and test in Europe
A novel criticality computation method in statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Efficient computation of the worst-delay corner
Proceedings of the conference on Design, automation and test in Europe
Fast second-order statistical static timing analysis using parameter dimension reduction
Proceedings of the 44th annual Design Automation Conference
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Design-silicon timing correlation: a data mining perspective
Proceedings of the 44th annual Design Automation Conference
Confidence scalable post-silicon statistical delay prediction under process variations
Proceedings of the 44th annual Design Automation Conference
A framework for accounting for process model uncertainty in statistical static timing analysis
Proceedings of the 44th annual Design Automation Conference
Statistical leakage power minimization using fast equi-slack shell based optimization
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric yield analysis and optimization in leakage dominated technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Monte-Carlo driven stochastic optimization framework for handling fabrication variability
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Clustering based pruning for statistical criticality computation under process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing budgeting under arbitrary process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Principle Hessian direction based parameter reduction with process variation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compact modeling of variational waveforms
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A methodology for timing model characterization for statistical static timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Robust gate sizing via mean excess delay minimization
Proceedings of the 2008 international symposium on Physical design
Variations, margins, and statistics
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2008 international symposium on Physical design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Statistical gate delay model for multiple input switching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Static timing: back to our roots
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
VariaSim: simulating circuits and systems in the presence of process variability
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Invited paper: Variability in nanometer CMOS: Impact, analysis, and minimization
Integration, the VLSI Journal
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Utilizing redundancy for timing critical interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parameterized timing analysis with general delay models and arbitrary variation sources
Proceedings of the 45th annual Design Automation Conference
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Proceedings of the 45th annual Design Automation Conference
Efficient Monte Carlo based incremental statistical timing analysis
Proceedings of the 45th annual Design Automation Conference
A framework for block-based timing sensitivity analysis
Proceedings of the 45th annual Design Automation Conference
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution
Proceedings of the 45th annual Design Automation Conference
Modeling crosstalk in statistical static timing analysis
Proceedings of the 45th annual Design Automation Conference
Signal probability based statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Optimal margin computation for at-speed test
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Latch modeling for statistical timing analysis
Proceedings of the conference on Design, automation and test in Europe
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
FPCNA: a field programmable carbon nanotube array
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Efficient block-based parameterized timing analysis covering all potentially critical paths
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Adjustment-based modeling for statistical static timing analysis with high dimension of variability
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Practical, fast Monte Carlo statistical static timing analysis: why and how
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Decoupling capacitance allocation for timing with statistical noise model and timing analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Statistical path selection for at-speed test
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A statistical approach for full-chip gate-oxide reliability analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variation-aware resource sharing and binding in behavioral synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Accelerating statistical static timing analysis using graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Accounting for non-linear dependence using function driven component analysis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Generating realistic stimuli for accurate power grid analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Statistical analysis of circuit timing using majorization
Communications of the ACM - A Blind Person's Interaction with Technology
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analog Integrated Circuits and Signal Processing
Variation-aware multimetric optimization during gate sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Statistical ordering of correlated timing quantities and its application for path ranking
Proceedings of the 46th Annual Design Automation Conference
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adjustment-based modeling for timing analysis under variability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for scalable postsilicon statistical delay prediction under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal test margin computation for at-speed structural test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pre-ATPG path selection for near optimal post-ATPG process space coverage
Proceedings of the 2009 International Conference on Computer-Aided Design
Quantifying robustness metrics in parameterized static timing analysis
Proceedings of the 2009 International Conference on Computer-Aided Design
Timing model extraction for sequential circuits considering process variations
Proceedings of the 2009 International Conference on Computer-Aided Design
Voltage binning under process variation
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the 2009 International Conference on Computer-Aided Design
Post-fabrication measurement-driven oxide breakdown reliability prediction and management
Proceedings of the 2009 International Conference on Computer-Aided Design
DeltaSyn: an efficient logic difference optimizer for ECO synthesis
Proceedings of the 2009 International Conference on Computer-Aided Design
Design and evaluation of a carbon nanotube-based programmable architecture
International Journal of Parallel Programming
Capturing post-silicon variations using a representative critical path
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing variation-aware high-level synthesis considering accurate yield computation
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Effective corner-based techniques for variation-aware IC timing verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
Speedpath analysis under parametric timing models
Proceedings of the 47th Design Automation Conference
Transistor sizing of custom high-performance digital circuits with parametric yield considerations
Proceedings of the 47th Design Automation Conference
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using randomization to cope with circuit uncertainty
Proceedings of the Conference on Design, Automation and Test in Europe
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design time body bias selection for parametric yield improvement
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
On confidence in characterization and application of variation models
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of FMAX and ISB in microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical timing yield optimization by gate sizing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast estimation of timing yield bounds for process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing variation-aware scheduling and resource binding in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 48th Design Automation Conference
A fast approach for static timing analysis covering all PVT corners
Proceedings of the 48th Design Automation Conference
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Interpreting SSTA results with correlation
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Optimal statistical chip disposition
Proceedings of the International Conference on Computer-Aided Design
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers
Proceedings of the International Conference on Computer-Aided Design
Active learning framework for post-silicon variation extraction and test cost reduction
Proceedings of the International Conference on Computer-Aided Design
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods
Proceedings of the International Conference on Computer-Aided Design
A lower bound computation method for evaluation of statistical design techniques
Proceedings of the International Conference on Computer-Aided Design
Delay-correlation-aware SSTA based on conditional moments
Microelectronics Journal
Statistical critical path analysis considering correlations
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Reversible statistical max/min operation: concept and applications to timing
Proceedings of the 49th Annual Design Automation Conference
An accurate sparse-matrix based framework for statistical static timing analysis
Integration, the VLSI Journal
Computation of joint timing yield of sequential networks considering process variations
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
A statistical approach to the timing-yield optimization of pipeline circuits
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Timing yield analysis considering process-induced temperature and supply voltage variations
Microelectronics Journal
On the computation of criticality in statistical timing analysis
Proceedings of the International Conference on Computer-Aided Design
A dynamic method for efficient random mismatch characterization of standard cells
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TAU 2013 variation aware timing analysis contest
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Thermal stress aware 3D-IC statistical static timing analysis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Proceedings of the 50th Annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Order statistics for correlated random variables and its application to at-speed testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Integration, the VLSI Journal
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Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.