Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
A reconfigurable design-for-debug infrastructure for SoCs
Proceedings of the 43rd annual Design Automation Conference
Refined statistical static timing analysis through
Proceedings of the 43rd annual Design Automation Conference
Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design-silicon timing correlation: a data mining perspective
Proceedings of the 44th annual Design Automation Conference
Confidence scalable post-silicon statistical delay prediction under process variations
Proceedings of the 44th annual Design Automation Conference
Variation-aware adaptive voltage scaling system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Path selection for monitoring unexpected systematic timing effects
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesizing a representative critical path for post-silicon delay prediction
Proceedings of the 2009 international symposium on Physical design
Tunable sensors for process-aware voltage scaling
Proceedings of the International Conference on Computer-Aided Design
Capturing post-silicon variation by layout-aware path-delay testing
Proceedings of the Conference on Design, Automation and Test in Europe
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In nanoscale technologies that experience large levels of process variation, post-silicon adaptation is an important step in circuit design. These adaptation techniques are often based on measurements of a replica of the nominal critical path, whose variations are intended to reflect those of the entire circuit after manufacturing. For realistic circuits, where the number of critical paths can be large, the notion of using a single critical path is too simplistic. This paper overcomes this problem by introducing the idea of synthesizing a representative critical path (RCP), which captures these complexities of the variations. We first prove that the requirement on the RCP is that it should be highly correlated with the circuit delay. Next, we present three novel algorithms to automatically build the RCP. Our experimental results demonstrate that over a number of samples of manufactured circuits, the delay of the RCP captures the worst case delay of the manufactured circuit. The average prediction error of all circuits is shown to be below 2.8% for all three approaches. For both our approach and the critical path replica method, it is essential to guard-band the prediction to ensure pessimism: on average our approach requires a guard band 31% smaller than for the critical path replica method.