Correlation-aware statistical timing analysis with non-gaussian delay distributions

Authors:
Yaping Zhan;Andrzej J. Strojwas;Xin Li;Lawrence T. Pileggi;David Newmark;Mahesh Sharma
Affiliations:
Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Carnegie Mellon University, Pittsburgh, PA;Advanced Micro Devices Inc., Austin, TX;Advanced Micro Devices Inc., Austin, TX
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

Citing 8
Cited 53

A general probabilistic framework for worst case timing analysis

Proceedings of the 39th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits

Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis

Proceedings of the 41st annual Design Automation Conference
STAC: statistical timing analysis with correlation

Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Using Bounds

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Asymptotic probability extraction for non-normal distributions of circuit performance

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis

Proceedings of the 2006 international symposium on Physical design
Statistical critical path analysis considering correlations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis

Proceedings of the 43rd annual Design Automation Conference
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty

Proceedings of the 43rd annual Design Automation Conference
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation

Proceedings of the 2007 international symposium on Physical design
Practical variation-aware interconnect delay and slew analysis for statistical timing verification

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An accurate sparse matrix based framework for statistical static timing analysis

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A new statistical max operation for propagating skewness in statistical timing analysis

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Performance-oriented statistical parameter reduction of parameterized systems via reduced rank regression

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs

Proceedings of the conference on Design, automation and test in Europe
Fast second-order statistical static timing analysis using parameter dimension reduction

Proceedings of the 44th annual Design Automation Conference
Non-linear statistical static timing analysis for non-Gaussian variation sources

Proceedings of the 44th annual Design Automation Conference
FPGA Design Automation: A Survey

Foundations and Trends in Electronic Design Automation
Statistical performance modeling and optimization

Foundations and Trends in Electronic Design Automation
A quadratic modeling-based framework for accurate statistical timing analysis considering correlations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient method for statistical circuit simulation

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A methodology for timing model characterization for statistical static timing analysis

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Robust gate sizing via mean excess delay minimization

Proceedings of the 2008 international symposium on Physical design
Statistical gate delay model for multiple input switching

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Non-Gaussian statistical timing models of die-to-die and within-die parameter variations for full chip analysis

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
VariaSim: simulating circuits and systems in the presence of process variability

ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
Parameterized timing analysis with general delay models and arbitrary variation sources

Proceedings of the 45th annual Design Automation Conference
System-level throughput analysis for process variation aware multiple voltage-frequency island designs

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental criticality and yield gradients

Proceedings of the conference on Design, automation and test in Europe
Latch modeling for statistical timing analysis

Proceedings of the conference on Design, automation and test in Europe
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Process variability-aware transient fault modeling and analysis

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Synthesizing a representative critical path for post-silicon delay prediction

Proceedings of the 2009 international symposium on Physical design
Process variation mitigation via post silicon clock tuning

Proceedings of the 19th ACM Great Lakes symposium on VLSI
Statistical static timing analysis: A survey

Integration, the VLSI Journal
Fast variational interconnect delay and slew computation using quadratic models

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Gaussian mixture model for statistical timing analysis

Proceedings of the 46th Annual Design Automation Conference
Non-Gaussian statistical timing analysis using second-order polynomial fitting

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An on-the-fly parameter dimension reduction approach to fast second-order statistical static timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A framework for scalable postsilicon statistical delay prediction under process variations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal test margin computation for at-speed structural test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Binning optimization based on SSTA for transparently-latched circuits

Proceedings of the 2009 International Conference on Computer-Aided Design
Timing model extraction for sequential circuits considering process variations

Proceedings of the 2009 International Conference on Computer-Aided Design
Virtual probe: a statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits

Proceedings of the 2009 International Conference on Computer-Aided Design
Capturing post-silicon variations using a representative critical path

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation

Proceedings of the Conference on Design, Automation and Test in Europe
On hierarchical statistical static timing analysis

Proceedings of the Conference on Design, Automation and Test in Europe
Fast estimation of timing yield bounds for process variations

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast statistical timing analysis for circuits with post-silicon tunable clock buffers

Proceedings of the International Conference on Computer-Aided Design
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods

Proceedings of the International Conference on Computer-Aided Design
Statistical critical path analysis considering correlations

PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Statistical Timing and Power Optimization of Architecture and Device for FPGAs

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
An accurate sparse-matrix based framework for statistical static timing analysis

Integration, the VLSI Journal
Computation of joint timing yield of sequential networks considering process variations

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Hardware/software approaches for reducing the process variation impact on instruction fetches

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
The effect of random dopant fluctuations on logic timing at low voltage

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fourier series approximation for max operation in non-Gaussian and quadratic statistical static timing analysis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Process variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The Non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In this paper, we present an efficient block-based statistical timing analysis approach with linear complexity with respect to the circuit size, which can accurately predict Non-Gaussian delay distributions from realistic nonlinear gate and interconnect delay models. This approach accounts for all correlations, from manufacturing process dependence, to re-convergent circuit paths to produce more accurate statistical timing predictions. With this approach, circuit designers can have increased confidence in the variation estimates, at a low additional computation cost.