Hierarchical algorithms for assessing probabilistic constraints on system performance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
Estimating probabilistic timing performance for real-time embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Design for Variability in DSM Technologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Variability and energy awareness: a microarchitecture-level perspective
Proceedings of the 42nd annual Design Automation Conference
Correlation-aware statistical timing analysis with non-gaussian delay distributions
Proceedings of the 42nd annual Design Automation Conference
System level power and performance modeling of GALS point-to-point communication interfaces
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Process Variation Tolerant 3T1D-Based Cache Architectures
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Sunflower: full-system, embedded, microarchitecture evaluation
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors
Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis
Exploring the effects of on-chip thermal variation on high-performance multicore architectures
ACM Transactions on Architecture and Code Optimization (TACO)
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Process variation aware performance modeling and dynamic power management for multi-core systems
Proceedings of the International Conference on Computer-Aided Design
Recovery-based design for variation-tolerant SoCs
Proceedings of the 49th Annual Design Automation Conference
VarEMU: an emulation testbed for variability-aware software
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure
Computers and Electrical Engineering
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The increasing variability in manufacturing process parameters is expected to lead to significant performance degradation in deep submicron technologies. Multiple Voltage-Frequency Island (VFI) design styles with fine-grained, process-variation aware clocking have recently been shown to possess increased immunity to manufacturing process variations. In this article, we propose a theoretical framework that allows designers to quantify the performance improvement that is to be expected if they were to migrate from a fully synchronous design to the proposed multiple VFI design style. Specifically, we provide techniques to efficiently and accurately estimate the probability distribution of the execution rate (or throughput) of both single and multiple VFI systems under the influence of manufacturing process variations. Finally, using an MPEG-2 encoder benchmark, we demonstrate how the proposed analysis framework can be used by designers to make architectural decisions such as the granularity of VFI domain partitioning based on the throughput constraints their systems are required to satisfy.