A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks

Authors:
Animesh Datta;Swarup Bhunia;Nilanjan Banerjee;Kaushik Roy
Affiliations:
Purdue University;Purdue University;Purdue University;Purdue University
Venue:
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Year:
2005

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Abstract

We propose an adaptive scalable architecture suitable for performing real-time algorithm-specific tasks. The architecture is based on Globally Asynchronous and Locally Synchronous (GALS) design paradigm. We demonstrate that for different real-time commercial applications with algorithm-specific jobs like online transaction processing, Fourier transform etc., the proposed architecture allows dynamic load-balancing and adaptive inter-task voltage scaling. The architecture can also detect process-shifts for the individual processing units and determine their appropriate operating conditions. Simulation results for two representative applications show that for a random job distribution, we obtain up to 67% improvement in MOPS/W (millions of operations per second per watt) over a fully synchronous implementation.