Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Voltage scheduling problem for dynamically variable voltage processors
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Timekeeping in the memory system: predicting and optimizing memory behavior
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Compile-time dynamic voltage scaling settings: opportunities and limits
PLDI '03 Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Profile-based dynamic voltage and frequency scaling for a multiple clock domain microprocessor
Proceedings of the 30th annual international symposium on Computer architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP
ACM Transactions on Architecture and Code Optimization (TACO)
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
IEEE Transactions on Computers
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Runtime identification of microprocessor energy saving opportunities
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Combined circuit and architectural level variable supply-voltage scaling for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Combining compiler and operating system support for energy efficient I/O on embedded platforms
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Energy-efficient instruction scheduling utilizing cache miss information
MEDEA '05 Proceedings of the 2005 workshop on MEmory performance: DEaling with Applications , systems and architecture
VirtualPower: coordinated power management in virtualized enterprise systems
Proceedings of twenty-first ACM SIGOPS symposium on Operating systems principles
Proceedings of the 45th annual Design Automation Conference
Hardware-compiler co-design for adjustable data power savings
Microprocessors & Microsystems
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Reducing branch misprediction penalties via adaptive pipeline scaling
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Interval-based models for run-time DVFS orchestration in superscalar processors
Proceedings of the 7th ACM international conference on Computing frontiers
Proceedings of the 7th ACM international conference on Computing frontiers
Fine-grained DVFS using on-chip regulators
ACM Transactions on Architecture and Code Optimization (TACO)
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
Dynamic processor throttling for power efficient computations
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Effective dynamic voltage scaling through CPU-Boundedness detection
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
| Hi-index | 0.00 |
Energy-efficient processor design is becoming moreand more important with technology scaling and with highperformance requirements. Supply-voltage scaling is anefficient way to reduce energy by lowering the operatingvoltage and the clock frequency of processorsimultaneously. We propose a variable supply-voltagescaling (VSV) technique based on the following keyobservation: upon an L2 miss, the pipeline performs someindependent computations but almost always ends upstalling and waiting for data, despite out-of-order issueand other latency-hiding techniques. Therefore, during anL2 miss we scale down the supply voltage of certainsections of the processor in order to reduce powerdissipation while it carries on the independentcomputations at a lower speed. However, operating at alower speed may degrade performance, if there aresufficient independent computations to overlap with the L2miss. Similarly, returning to high speed may degradepower savings, if there are multiple outstanding missesand insufficient independent computations to overlap withthem. To avoid these problems, we introduce two statemachines that track parallelism on-the-fly, and we scalethe supply voltage depending on the level of parallelism.We also consider circuit-level complexity concerns whichlimit VSV to two supply voltages, stability and signal-propagationspeed issues which limit how fast VSV maytransition between the voltages, and energy overheadfactors which disallow supply-voltage scaling of largeRAM structures such as caches and register file. Oursimulations show that VSV achieves an average of 20.7%total processor power reduction with 2.0% performancedegradation in an 8-way, out-of-order-issue processor thatimplements deterministic clock gating and softwareprefetching, for those SPEC2K benchmarks that have highL2 miss rates. Averaging across all the benchmarks, VSVreduces total processor power by 7.0% with 0.9%performance degradation.