Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Deterministic Clock Gating for Microprocessor Power Reduction
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Low Power Adder with Adaptive Supply Voltage
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Trifecta: a nonspeculative scheme to exploit common, data-dependent subcritical paths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose a novel low-power Carry-Select Adder (CSA) design called Cascaded CSA (C2SA). Based on the prediction of the critical path delay of current operation, C2SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C2SA in 180nm Technology show that C2SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) Latency Per Operation (LPO) compared to standard CSA