Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Telescopic units: increasing the average throughput of pipelined designs by adaptive latency control
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low Power Adder with Adaptive Supply Voltage
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Voltage scalable high-speed robust hybrid arithmetic units using adaptive clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose a design methodology for low-power, high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.