Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Low Power Adder with Adaptive Supply Voltage
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Low-power process-variation tolerant arithmetic units using input-based elastic clocking
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Comparison of high-performance VLSI adders in the energy-delay space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proposed low power, high speed adder-based 65-nm Square root circuit
Microelectronics Journal
An efficient EPI and energy consumption of 32 bit ALU using Shannon theorem based adder approach
WSEAS Transactions on Circuits and Systems
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Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it also degrades robustness. Recently, researchers have proposed novel design technique for linear time complexity adders that maintain high yield and high clock frequency even at scaled supply voltage. The idea is based on the fact that the critical paths of arithmetic units are exercised rarely. The technique (a) predicts the set of critical paths, (b) reduces the supply voltage to operate non-critical paths at rated frequency, and; (c) avoids possible delay failures in the critical paths by dynamically stretching the clock period (to say, two-cycles assuming all standard operations are single-cycle), when they are activated. This allows circuits to operate at scaled supply with minimal performance degradation. The off-critical paths operate in single clock cycle while critical paths are operated in stretched clock period. Different classes of adders may benefit differently using such technique. For example, ripple carry adders can reap the benefits more effectively than say, tree adders (balanced paths). However, logic modification may ease the application of supply voltage scaling. In this paper, we explore various arithmetic units for possible use in high speed, high yield ALU design at scaled supply voltage with variable latency operation. We demonstrate that careful logic optimization of the existing arithmetic units indeed make them further suitable for supply voltage scaling with tolerable area overhead. Simulation results on different adder and multiplier topologies in BPTM 70nm technology show 18--60% extra improvement in power with only 2--8% increase in die-area at iso-yield. We also extend our studies to design low power and high yield multipliers. These optimized low power datapath units can be used to construct low power and robust ALU that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching.