Proposed low power, high speed adder-based 65-nm Square root circuit

Authors:
C. Senthilpari;Zuraida Irina Mohamad;S. Kavitha
Affiliations:
Faculty of Engineering and Technology, Multimedia University, Jalan Ayer Keroh lama, 75450 Melaka, Malaysia;Faculty of Engineering and Technology, Multimedia University, Jalan Ayer Keroh lama, 75450 Melaka, Malaysia;Faculty of Information and Communication Technology, Universiti Teknikal Malaysia Melaka (UTeM), Karung Berkunci No. 1752, Pejabat Pos Durian Tunggal, Durian Tunggal, 76109 Melaka, Malaysia
Venue:
Microelectronics Journal
Year:
2011

Citing 10
Cited 0

Computer arithmetic: algorithms and hardware designs

Computer arithmetic: algorithms and hardware designs
Computer Arithmetic: Principles, Architecture and Design

Computer Arithmetic: Principles, Architecture and Design
Multiple voltage and frequency scheduling for power minimization

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell

Microelectronics Journal
Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Designing high-speed adders in power-constrained environments

IEEE Transactions on Circuits and Systems II: Express Briefs
Custom circuit design as a driver of microprocessor performance

IBM Journal of Research and Development
A review of 0.18-µm full adder performances for tree structured arithmetic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and comparison on full adder block in submicron technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper focuses on the design of a 1-bit full adder circuit using Shannon's theorem and adder-based non-Restoring and Restoring Square Rooter circuits. The proposed adder and Square Rooter schematics were developed using DSCH2 CAD tool, and their layouts were generated with Microwind 3 VLSI CAD tool. The Square Rooter circuits were analysed using standard CMOS 65-nm features with a corresponding voltage of 0.7V. BSIM 4 was used to analyse the parameters. The proposed adder-based Square Rooter simulated results of the proposed adder with those of CPL, Static Energy Recovery Full (SERF), and CMOS adder cell-based Square Rooter circuits; the proposed adder-based Square Rooter circuit gives better results than the other adder-based Square Rooter circuits. We then compared the results with published results and observed that the proposed adder cell-based Square Rooter circuit dissipates lower power, responds faster, and has a higher EPI and higher throughput.