Designing high-speed adders in power-constrained environments

Authors:
Fabio Frustaci;Marco Lanuzza;Paolo Zicari;Stefania Perri;Pasquale Corsonello
Affiliations:
Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Italy;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Italy
Venue:
IEEE Transactions on Circuits and Systems II: Express Briefs
Year:
2009

Citing 7
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Abstract

Data-driven dynamic logic (D3L) is very efficient when low-power constraints are mandatory. Unfortunately, this advantage is typically obtained at the expense of speed performances. This paper presents a novel technique to realize D3L parallel prefix tree adders without significantly compromising speed performance. When applied to a 64-bit Kogge-Stone adder realized with 90-nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed technique leads to an energy-delay product that is 29% and 21% lower than its standard domino logic and conventional D3L counterparts, respectively. It also shows a worst case delay tbat is 10% lower than that of the D3L approach and only 5% higher than that of the conventional domino logic.