Comparison of high-performance VLSI adders in the energy-delay space

Authors:
Vojin G. Oklobdzija;Bart R. Zeydel;Hoang Q. Dao;Sanu Mathew;Ram Krishnamurthy
Affiliations:
Advanced Computer Systems Engineering Laboratory, Electrical and Computer Engineering Department, University of California, Davis, CA;Advanced Computer Systems Engineering Laboratory, Electrical and Computer Engineering Department, University of California, Davis, CA;Advanced Computer Systems Engineering Laboratory, Electrical and Computer Engineering Department, University of California, Davis, CA;Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR;Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

In this paper, wemotivate the concept of comparing very large scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a need to make appropriate selection at the beginning of the design process. The estimation is quick, not requiring extensive simulation or use of computer-aided design tools, yet sufficiently accurate to provide guidance through various choices in the design process. We demonstrate the accuracy of the method by applying it to examples of high-performance 32- and 64-badders in 100- and 130-nm CMOS technologies.