Energy efficient implementation of parallel CMOS multipliers with improved compressors

Authors:
Dursun Baran;Mustafa Aktan;Vojin G. Oklobdzija
Affiliations:
University of Texas at Dallas, Richardson, TX, USA;University of Texas at Dallas, Richardson, TX, USA;University of Texas at Dallas, Richardson, TX, USA
Venue:
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Year:
2010

Citing 7
Cited 1

Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal Circuits for Parallel Multipliers

IEEE Transactions on Computers
Performance analysis of low-power 1-Bit CMOS full adder cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach

IEEE Transactions on Computers
Evaluation of Booth's algorithm for implementation in parallel multipliers

ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
A 40-ns 17-Bit by 17-Bit Array Multiplier

IEEE Transactions on Computers
Comparison of high-performance VLSI adders in the energy-delay space

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Improved CMOS (4;2) compressor designs for parallel multipliers

Computers and Electrical Engineering

Quantified Score

Hi-index	0.00

Visualization

Abstract

Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and Non-Booth multipliers are analyzed in energy and delay space under varying constraints. It is shown that Non-Booth multipliers start to become more energy efficient for strict delay targets. In addition, novel 3:2 and 4:2 compressors are presented to save energy at the same target delay. The proposed compressors provide up to 20% energy reduction depending on the target delay at 65nm CMOS technology. Non-Booth multiplier implemented with the proposed compressors provides performance advantage as the voltage is scaled from its nominal value. Further, we examined all designs in 45nm, 32nm and 22nm CMOS technology nodes.