IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Prediction of interconnect fan-out distribution using Rent's rule
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Integration, the VLSI Journal
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
CMOS full-adders for energy-efficient arithmetic applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We propose three new (4;2) compressors via improving best previous designs by replacing an integral portion of relevant logical circuits by an optimized CMOS full-adder. Two other new (4;2) compressors are also proposed based on new interpretation of logical equations that describe the corresponding functionality. The key design point is to use an available signal, in the sum path, for carry generation. All the proposed and referenced designs are evaluated by exhaustive HSPICE simulations at various temperatures, voltage scaling situations, load capacitances, and presence of process variation using the post-layout CMOS library of standard cell. These experiences show performance improvements, compared to the best of reference designs, in terms of delay (5%), power (16%), and PDP (26%), respectively. To evaluate the studied and new (4;2) compressors in a more practical environment, we utilized them for implementation of 54x54-bit parallel multipliers. Experimental results via MAGMA design tools confirmed the results that we achieved for isolated single (4;2) compressors.