Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An alternative logic approach to implement high-speed low-power full adder cells
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Energy-Efficient, High Performance Circuits for Arithmetic Units
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
ASIC Implimentation of 1 Bit Full Adder
ICETET '08 Proceedings of the 2008 First International Conference on Emerging Trends in Engineering and Technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved CMOS (4;2) compressor designs for parallel multipliers
Computers and Electrical Engineering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0.18-µm CMOS technology, and were tested using a comprehensive testbench that allowed to measure the current taken from the full-adder inputs, besides the current provided from the power-supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.