An alternative logic approach to implement high-speed low-power full adder cells

Authors:
Mariano Aguirre;Monico Linares
Affiliations:
INAOE-Mexico, Puebla, Mexico;INAOE-Mexico, Puebla, Mexico
Venue:
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Year:
2005

Citing 2
Cited 2

Principles of CMOS VLSI design: a systems perspective

Principles of CMOS VLSI design: a systems perspective
Performance analysis of low-power 1-Bit CMOS full adder cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Simple exact algorithm for transistor sizing of low-power high-speed arithmetic circuits

VLSI Design
CMOS full-adders for energy-efficient arithmetic applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

This paper presents a high-speed low-power 1-bit full adder cell designed upon an alternative logic structure to derive the SUM and CARRY outputs. Hspice and Nanosim simulations show that this full adder cell designed using a 0.35μm CMOS technology and supplied with 3.3V, exhibits delay and power dissipation around 720ps and 840μW, respectively. These features reflect an overall improvement of 30% in the power-delay metric, when compared with the performance of other realizations recently published as well featured cells for low-power applications.