Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A survey of optimization techniques targeting low power VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A New Low-Voltage Full Adder Circuit
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
An alternative logic approach to implement high-speed low-power full adder cells
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Journal of VLSI Signal Processing Systems
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed gate level synchronous full adder designs
WSEAS Transactions on Circuits and Systems
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal
A delay improved gate level full adder design
ECC'09 Proceedings of the 3rd international conference on European computing conference
A fast and power-area-efficient accumulator for flying-adder frequency synthesizer
IEEE Transactions on Circuits and Systems Part I: Regular Papers
A low power gate level full adder module
ASMCSS'09 Proceedings of the 3rd International Conference on Applied Mathematics, Simulation, Modelling, Circuits, Systems and Signals
Proceedings of the International Conference and Workshop on Emerging Trends in Technology
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
ECS'10/ECCTD'10/ECCOM'10/ECCS'10 Proceedings of the European conference of systems, and European conference of circuits technology and devices, and European conference of communications, and European conference on Computer science
A micropower low-voltage multiplier with reduced spurious switching
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A review of 0.18-µm full adder performances for tree structured arithmetic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A standard cell based synchronous dual-bit adder with embedded carry look-ahead
WSEAS Transactions on Circuits and Systems
High-speed full adder based on minority function and bridge style for nanoscale
Integration, the VLSI Journal
CMOS full-adders for energy-efficient arithmetic applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power and high performance dynamic CMOS XOR/XNOR gate design
Microelectronic Engineering
Logic style comparison for ultra low power operation in 65nm technology
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Design of 9-transistor single bit full adder
Proceedings of the Second International Conference on Computational Science, Engineering and Information Technology
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
Integration, the VLSI Journal
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
Integration, the VLSI Journal
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A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.