IEEE Transactions on Computers
Achieving 550 MHz in an ASIC methodology
Proceedings of the 38th annual Design Automation Conference
A semi-custom design flow in high-performance microprocessor design
Proceedings of the 38th annual Design Automation Conference
Performance analysis of low-power 1-Bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimized power-delay curve generation for standard cell ICs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An architecture of a high-speed digital hologram generator based on FPGA
Journal of Systems Architecture: the EUROMICRO Journal
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This paper proposes an innovative domain-specific cell based ASIC design flow to narrow the performance gap between the full custom ASIC design method and conventional standard-cell based ASIC design method. The flow can improve the design performance and still preserve the efficiency of the standard ASIC design flow. Targeting on digital signal processing applications, a domain-specific cell library is provided to augment of standard cell libraries. Experimental results of designing macros such as FFT, FIR etc. are shown in the paper. Based on this methodology a 64-tap FFT can achieve up to 24X performance improvement,with the Power 脳 Delay 脳 Area (PDA) criteria, over the conventional designed ASICs.