Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Custom S/390 G5 and G6 microprocessors
IBM Journal of Research and Development
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
Overview of continuous optimization advances and applications to circuit tuning
Proceedings of the 2001 international symposium on Physical design
Proceedings of the 2003 international symposium on Physical design
Optimized power-delay curve generation for standard cell ICs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
A Domain-Specific Cell Based ASIC Design Methodology for Digital Signal Processing Applications
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Efficient timing closure without timing driven placement and routing
Proceedings of the 41st annual Design Automation Conference
Optimization of circuit trajectories: an auxiliary network approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Structured and tuned array generation (STAG) for high-performance random logic
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The opportunity cost of low power design: a case study in circuit tuning
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
Power reduction via separate synthesis and physical libraries
Proceedings of the 48th Design Automation Conference
Efficient post-layout power-delay curve generation
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Hi-index | 0.00 |
In this paper we present techniques shown to significantly enhance the custom circuit design process typical of high-performance microprocessors. This methodology combines flexible custom circuit design with automated tuning and physical design tools to provide new opportunities to optimized design throughout the development cycle.