Global convergence of a class of trust region algorithms for optimization with simple bounds
SIAM Journal on Numerical Analysis
SIAM Journal on Numerical Analysis
Incremental event-driven simulation of digital FET circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Circuit optimization via adjoint Lagrangians
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Graph Theory With Applications
Graph Theory With Applications
JiffyTune: circuit optimization using time-domain sensitivities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Overview of continuous optimization advances and applications to circuit tuning
Proceedings of the 2001 international symposium on Physical design
A semi-custom design flow in high-performance microprocessor design
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Timing model extraction of hierarchical blocks by graph reduction
Proceedings of the 39th annual Design Automation Conference
Slope propagation in static timing analysis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
On the signal bounding problem in timing analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Time Budgeting in a Wireplanning Context
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Optimization of circuit trajectories: an auxiliary network approach
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Large-scale nonlinear optimization in circuit tuning
Future Generation Computer Systems
Timing model reduction for hierarchical timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design methods for attaining IBM System z9 processor cycle-time goals
IBM Journal of Research and Development
Static Timing Model Extraction for Combinational Circuits
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
The opportunity cost of low power design: a case study in circuit tuning
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Fast and accurate statistical criticality computation under process variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The circuit and physical design of the POWER4 microprocessor
IBM Journal of Research and Development
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
IBM Journal of Research and Development
Large-scale nonlinear optimization in circuit tuning
Future Generation Computer Systems
Hot-and-Cold: using criticality in the design of energy-efficient caches
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
NBTI-aware circuit node criticality computation
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Static circuit optimization implies sizing of transistors and wires on a static timing basis, taking into account all paths through a circuit. Previous methods of formulating static circuit optimization produce problem statements that are very large and contain inherent redundancy and degeneracy. In this paper, a method of manipulating the timing formulation is presented which produces a dramatically more compact optimization problem, and reduces redundancy and degeneracy. The circuit optimization is therefore more efficient and effective. Numerical results to demonstrate these improvements are presented.