Clique partitions, graph compression and speeding-up algorithms
STOC '91 Proceedings of the twenty-third annual ACM symposium on Theory of computing
On edge perfectness and classes of bipartite graphs
Discrete Mathematics
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Timing model extraction of hierarchical blocks by graph reduction
Proceedings of the 39th annual Design Automation Conference
Representing Graph Metrics with Fewest Edges
STACS '03 Proceedings of the 20th Annual Symposium on Theoretical Aspects of Computer Science
Static Timing Model Extraction for Combinational Circuits
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Timing model extraction for sequential circuits considering process variations
Proceedings of the 2009 International Conference on Computer-Aided Design
A hierarchical approach towards system level static timing verification of SoCs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
On hierarchical statistical static timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, each functional block is characterized into an abstract timing model. The complexity of analysis is linear to the number of edges in the abstract timing model for timing propagation. We propose a biclique-star replacement technique to minimize the number of edges in the timing model. The experiments on industry test cases show that by allowing acceptable errors, the proposed algorithm can largely reduce the number of edges in the timing model.