ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Timing model extraction of hierarchical blocks by graph reduction
Proceedings of the 39th annual Design Automation Conference
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
IEEE Design & Test
Timing model reduction for hierarchical timing analysis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Delay abstraction in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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For large circuits, static timing analysis (STA) needs to be performed in a hierarchical manner to achieve higher performance in arrival time propagation. In hierarchical STA, efficient and accurate timing models of sub-modules need to be created. We propose a timing model extraction method that significantly reduces the size of timing models without losing any accuracy by removing redundant timing information. Circuit components which do not contribute to the delay of any input to output pair are removed. The proposed method is deterministic. Compared to the original models, the numbers of edges and vertices of the resulting timing models are reduced by 84% and 85% on average, respectively, which are significantly more than the results achieved by other methods.