Timing model extraction of hierarchical blocks by graph reduction

Authors:
Cho W. Moon;Harish Kriplani;Krishna P. Belkhale
Affiliations:
Cadence Design Systems, San Diego, CA;Cadence Design Systems, San Diego, CA;Cadence Design Systems, San Diego, CA
Venue:
Proceedings of the 39th annual Design Automation Conference
Year:
2002

Citing 3
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Abstract

Timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from gate-level netlist by reducing a timing graph. Previous methods of generating timing models sacrificed accuracy and/or did not scale well with design size. The proposed method is simple, yet it provides model accuracy including arbitrary levels of latch time borrowing and capability to support timing constraints that span multiple blocks. Also, cpu and memory resources required to generate the model scale well with size of the circuit. The generated model can provide a capacity improvement in timing verification by more than two orders of magnitude.