Signal delay in RC tree networks
DAC '81 Proceedings of the 18th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Timing verification system based on delay time hierarchical nature
DAC '82 Proceedings of the 19th Design Automation Conference
SIMULATION TOOLS FOR DIGITAL LSI DESIGN
SIMULATION TOOLS FOR DIGITAL LSI DESIGN
Analysis and design of latch-controlled synchronous digital circuits
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Timing verification on a 1.2M-device full-custom CMOS design
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analyzing cycle stealing on synchronous circuits with level-sensitive latches
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
TIM: a timing package for two-phase, level-clocked circuitry
DAC '93 Proceedings of the 30th international Design Automation Conference
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Timing model extraction of hierarchical blocks by graph reduction
Proceedings of the 39th annual Design Automation Conference
Transistor-level timing analysis using embedded simulation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI
EDTC '96 Proceedings of the 1996 European conference on Design and Test
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Pearl is a timing analyzer that has been used to verify both full custom VLSI and gate array designs. Rather than verify that a design meets a given clock timing, Pearl automatically determines the minimum error free clock period and duty cycles. Delay equations compiled for the circuit facilitate fast incremental analysis when false paths are blocked or transistor sizes are changed while optimizing the circuit. Pearl is one component of a large, tightly integrated set of design tools. This allows it to report delay paths graphically in the schematic editor, greatly improving interpretation of results over simple textual reports. Because it can handle networks that mix transistors and functional models it is able to accurately analyze circuits in which switch level timing models fail. We also describe transistor signal flow direction rules for CMOS circuits used to eliminate false paths.