SubGemini: identifying subcircuits using a fast subgraph isomorphism algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
VLSI timing simulation with selective dynamic regionization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
TETA: transistor-level engine for timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Proposal of a timing model for CMOS logic gates driving a CRC &pgr; load
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Transistor-level gate model based statistical timing analysis considering correlations
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.