Fundamentals of computer-aided circuit simulation
Fundamentals of computer-aided circuit simulation
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Mixed-Mode Simulation
ftd: an exact frequency to time domain conversion for reduced order RLC interconnect models
DAC '98 Proceedings of the 35th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Static timing analysis taking crosstallk into account
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Computing logic-stage delays using circuit simulation and symbolic elmore analysis
Proceedings of the 38th annual Design Automation Conference
Transistor-level timing analysis using embedded simulation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Direct transistor-level layout for digital blocks
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Piecewise quadratic waveform matching with successive chord iteration
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
MAPS: multi-algorithm parallel circuit simulation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fast circuit simulation on graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Parallel program performance modeling for runtime optimization of multi-algorithm circuit simulation
Proceedings of the 47th Design Automation Conference
On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation
Proceedings of the International Conference on Computer-Aided Design
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TETA is an interconnect-centric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor clusters and employs successive chord iterations to solve the resulting nonlinear equations. These algorithms permit the use of simple SIMO (single input multi-output) N-port interconnect models since macromodel passivity is not required. The successive chord analysis also enables TETA to avoid the N-port matrix factorization during nonlinear iterations and allows the use of simple table look-up models for MOS devices. Complex gates and nonlinear capacitors can be handled without loss of generality.