Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching

  • Authors:
  • Zhong Wang;Jianwen Zhu

  • Affiliations:
  • University of Toronto;University of Toronto

  • Venue:
  • DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
  • Year:
  • 2003

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Abstract

While fast timing analysis methods, such as asymptotic waveform evaluation (AWE), have been well established for linear circuits, the timing analysis for non-linear circuits, which are dominant in digital CMOS circuits, is usually performed by a SPICE like, time domain integration based approach, involving expensive Newton Raphson iterations at numerous time steps. In this paper, we propose a new technique that leads to the transient solution of charge/discharge paths with a complexity equivalent to only K DC operating point calculations, where K is the number of transistors along the path. This is accomplished by approximating each nodal voltage as a piecewise quadratic waveform, whose characteristics can be determined by matching the charge/discharge currents. Experiments on a wide range of circuits show that a 31.6 times speed-up over SPICE transient simulation with 10ps step size can be achieved, while maintaining an average accuracy of 99%.