Addressing high frequency effects in VLSI interconnects with full wave model and CFH
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Coping with RC(L) interconnect design headaches
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient full-wave electromagnetic analysis via model-order reduction of fast integral transforms
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Automatic netlist extraction for measurement-based characterization of off-chip interconnect
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Zeros and passivity of Arnoldi-reduced-order models for interconnect networks
DAC '97 Proceedings of the 34th annual Design Automation Conference
Lumped interconnect models via Gaussian quadrature
DAC '97 Proceedings of the 34th annual Design Automation Conference
Accurate and efficient macromodel of submicron digital standard cells
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Multipoint Padé approximation using a rational block Lanczos algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Circuit noise evaluation by Padé approximation based model-reduction techniques
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimization techniques for high-performance digital circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Simulation methods for RF integrated circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Tools and methodology for RF IC design
DAC '98 Proceedings of the 35th annual Design Automation Conference
h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reduced-order modelling of linear time-varying systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Error bounded Padé approximation via bilinear conformal transformation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A rank-one update method for efficient processing of interconnect parasitics in timing analysis
Proceedings of the 37th Annual Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
Projection frameworks for model reduction of weakly nonlinear systems
Proceedings of the 37th Annual Design Automation Conference
A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources
Proceedings of the 37th Annual Design Automation Conference
Passive model order reduction of multiport distributed interconnects
Proceedings of the 37th Annual Design Automation Conference
Practical considerations for passive reduction of RLC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient model reduction of interconnect via approximate system gramians
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Efficient and passive modeling of transmission lines by using differential quadrature method
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Hierarchical model order reduction for signal-integrity interconnect synthesis
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Balanced truncation with spectral shaping for RLC interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
An optimum fitting algorithm for generation of reduced-order models
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Estimation of power distribution in VLSI interconnects
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Novel interconnect modeling by using high-order compact finite difference methods
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Geometrically parameterized interconnect performance models for interconnect synthesis
Proceedings of the 2002 international symposium on Physical design
A factorization-based framework for passivity-preserving model reduction of RLC systems
Proceedings of the 39th annual Design Automation Conference
Signal integrity fault analysis using reduced-order modeling
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Mixed-Technology System-Level Simulation
Analog Integrated Circuits and Signal Processing
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Microelectronic Engineering
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Explicit gate delay model for timing evaluation
Proceedings of the 2003 international symposium on Physical design
Krylov subspace techniques for reduced-order modeling of large-scale dynamical systems
Applied Numerical Mathematics
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Robust and passive model order reduction for circuits containing susceptance elements
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient model order reduction via multi-node moment matching
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Efficient model order reduction including skin effect
Proceedings of the 40th annual Design Automation Conference
Model order reduction of nonuniform transmission lines using integrated congruence transform
Proceedings of the 40th annual Design Automation Conference
NORM: compact model order reduction of weakly nonlinear systems
Proceedings of the 40th annual Design Automation Conference
Analog and RF circuit macromodels for system-level analysis
Proceedings of the 40th annual Design Automation Conference
Piecewise polynomial nonlinear model reduction
Proceedings of the 40th annual Design Automation Conference
Closed-Form Crosstalk Noise Delay Metrics
Analog Integrated Circuits and Signal Processing
Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit Extraction
EDTC '96 Proceedings of the 1996 European conference on Design and Test
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Efficient Macromodeling for On-Chip Interconnects
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Crosstalk Aware Static Timing Analysis: A Two Step Approach
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
System Level Modeling of Microsystems Using Order Reduction Methods
Analog Integrated Circuits and Signal Processing
Krylov subspace methods for large-scale matrix problems in control
Future Generation Computer Systems - Selected papers on theoretical and computational aspects of structural dynamical systems in linear algebra and control
Improved model-order reduction by using spacial information in moments
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Poor Man's TBR: A Simple Model Reduction Scheme
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Direct Nonlinear Order Reduction with Variational Analysis
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting input information in a model reduction algorithm for massively coupled parasitic networks
Proceedings of the 41st annual Design Automation Conference
CAD challenges in BioMEMS design
Proceedings of the 41st annual Design Automation Conference
Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects
Proceedings of the 41st annual Design Automation Conference
Interconnect Macromodelling and Approximation of Matrix Exponent
Analog Integrated Circuits and Signal Processing
Analog Macromodeling using Kernel Methods
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A General S-Domain Hierarchical Network Reduction Algorithm
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Piecewise quadratic waveform matching with successive chord iteration
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Parametric reduced order modeling for interconnect analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Realizable parasitic reduction for distributed interconnects using matrix pencil technique
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Noise Macromodel for Radio Frequency Integrated Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Model-Order Reduction Based on PRONY's Method
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Transpose-free multiple Lanczos and its application in Padé approximation
Journal of Computational and Applied Mathematics
A complete methodology for an accurate static noise analysis
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Automated nonlinear Macromodelling of output buffers for high-speed digital applications
Proceedings of the 42nd annual Design Automation Conference
Operator-based model-order reduction of linear periodically time-varying systems
Proceedings of the 42nd annual Design Automation Conference
Piece-wise approximations of RLCK circuit responses using moment matching
Proceedings of the 42nd annual Design Automation Conference
Structure preserving reduction of frequency-dependent interconnect
Proceedings of the 42nd annual Design Automation Conference
Performance Simulation of a Microwave Micro-Electromechanical System Shunt Switch Using Chatoyant
Analog Integrated Circuits and Signal Processing
Parameter independent model order reduction
Mathematics and Computers in Simulation
EFFICIENT THERMAL SIMULATION FOR RUN-TIME TEMPERATURE TRACKING AND MANAGEMENT
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
SPRIM: structure-preserving reduced-order interconnect macromodeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Computation of signal threshold crossing times directly from higher order moments
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variational interconnect analysis via PMTBR
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Macromodelling oscillators using Krylov-subspace methods
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A frequency separation macromodel for system-level simulation of RF circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient Model Update for General Link-Insertion Networks
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Compact Reduced Order Modeling for Multiple-Port Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A more reliable reduction algorithm for behavioral model extraction
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient method for terminal reduction of interconnect circuits considering delay variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Expanding the frequency range of AWE via time shifting
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A sliding window scheme for accurate clock mesh analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Proceedings of the 43rd annual Design Automation Conference
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Random sampling of moment graph: a stochastic Krylov-reduction algorithm
Proceedings of the conference on Design, automation and test in Europe
SBPOR: second-order balanced truncation for passive order reduction of RLC circuits
Proceedings of the 44th annual Design Automation Conference
An efficient terminal and model order reduction algorithm
Integration, the VLSI Journal
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A nonlinear cell macromodel for digital applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
DeMOR: decentralized model order reduction of linear networks with massive ports
Proceedings of the 45th annual Design Automation Conference
Towards a more physical approach to gate modeling for timing, noise, and power
Proceedings of the 45th annual Design Automation Conference
Model-order reductions for MIMO systems using global Krylov subspace methods
Mathematics and Computers in Simulation
Multiple block structure-preserving reduced order modeling of interconnect circuits
Integration, the VLSI Journal
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Sparse implicit projection (SIP) for reduction of general many-terminal networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Statistical static timing analysis: A survey
Integration, the VLSI Journal
Analytical timing model for inductance-dominant interconnect based on traveling wave propagation
Microelectronics Journal
Fast variational interconnect delay and slew computation using quadratic models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
Stable parallelizable model order reduction for circuits with frequency-dependent elements
IEEE Transactions on Circuits and Systems Part I: Regular Papers
QLMOR: a new projection-based approach for nonlinear model order reduction
Proceedings of the 2009 International Conference on Computer-Aided Design
Numerical Simulation and Modelling of Electronic and Biochemical Systems
Foundations and Trends in Electronic Design Automation
Transpose-free multiple Lanczos and its application in Padé approximation
Journal of Computational and Applied Mathematics
Model reduction for large-scale dynamical systems via equality constrained least squares
Journal of Computational and Applied Mathematics
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Advanced methods for equivalence checking of analog circuits with strong nonlinearities
Formal Methods in System Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PABTEC: passivity-preserving balanced truncation for electrical circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Model order reduction for large LTI control systems
Journal of Computer and Systems Sciences International
Passive rational interpolation-based reduction via Carathéodory extension for general systems
IEEE Transactions on Circuits and Systems II: Express Briefs
Efficient model reduction of interconnects via double gramians approximation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Manifold construction and parameterization for nonlinear manifold-based model reduction
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Balanced truncation for time-delay systems via approximate Gramians
Proceedings of the 16th Asia and South Pacific Design Automation Conference
The Lanczos Method for Parameterized Symmetric Linear Systems with Multiple Right-Hand Sides
SIAM Journal on Matrix Analysis and Applications
A Framework for Reduced Order Modeling with Mixed Moment Matching and Peak Error Objectives
SIAM Journal on Scientific Computing
Parameter and State Model Reduction for Large-Scale Statistical Inverse Problems
SIAM Journal on Scientific Computing
Efficient simulation of nonuniform transmission lines using integrated congruence transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICS'06 Proceedings of the 10th WSEAS international conference on Systems
Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast waveform estimation (FWE) for timing analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Enhanced linearized reduced-order models for subsurface flow simulation
Journal of Computational Physics
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Interpolatory Projection Methods for Parameterized Model Reduction
SIAM Journal on Scientific Computing
Structure preserving reduced-order modeling of linear periodic time-varying systems
Proceedings of the International Conference on Computer-Aided Design
Krylov-Based Model Order Reduction of Time-delay Systems
SIAM Journal on Matrix Analysis and Applications
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
Interpolatory weighted-H2 model reduction
Automatica (Journal of IFAC)
ABCD-L: approximating continuous linear systems using boolean models
Proceedings of the 50th Annual Design Automation Conference
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatica (Journal of IFAC)
Parametric dominant pole algorithm for parametric model order reduction
Journal of Computational and Applied Mathematics
Journal of Electronic Testing: Theory and Applications
Mathematics and Computers in Simulation
| Hi-index | 0.05 |
In this paper, we introduce PVL, an algorithm for computing the Pade approximation of Laplace-domain transfer functions of large linear networks via a Lanczos process. The PVL algorithm has significantly superior numerical stability, while retaining the same efficiency as algorithms that compute the Pade approximation directly through moment matching, such as AWE and its derivatives. As a consequence, it produces more accurate and higher-order approximations, and it renders unnecessary many of the heuristics that AWE and its derivatives had to employ. The algorithm also computes an error bound that permits to identify the true poles and zeros of the original network. We present results of numerical experiments with the PVL algorithm for several large examples