Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Transient simulation of lossy interconnect
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
RICE: Rapid interconnect circuit evaluator
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A gate-delay model for high-speed CMOS circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Optimal equivalent circuits for interconnect delay calculations using moments
EURO-DAC '94 Proceedings of the conference on European design automation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
The Elmore delay as bound for RC trees with generalized input signals
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Numerical integration algorithms and asymptotic waveform evaluation (AWE)
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Timing Verification and Optimization for the PowerPCTM Processor Family
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A sparse image method for BEM capacitance extraction
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Determination of worst-case aggressor alignment for delay calculation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Equivalent Elmore delay for RLC trees
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Theoretical limits for signal reflections due to inductance for on-chip interconnections
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
An analytic calculation method for delay time of RC-class interconnects
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An efficient model for frequency-dependent on-chip inductance
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Closed-Form Crosstalk Noise Delay Metrics
Analog Integrated Circuits and Signal Processing
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Analytical Fast Timing Simulation of MOS Circuits Driving RC Interconnects
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Coupling Noise Analysis for VLIS and ULSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A two-directional Arnoldi process and its application to parametric model order reduction
Journal of Computational and Applied Mathematics
DSM interconnects: importance of inductance effects and corresponding range of length
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Physical interconnect effects have a dominant impact on today's deep submicron IC designs. In this tutorial paper we will describe the technology trends which have brought about this interconnect dominance, then consider some of the modeling and analysis approximations available for both pre- and post-layout interconnect design. This coverage will not be an exhaustive summary, but one that is primarily focused on moment-based analysis techniques, from the Elmore delay, to the more recent advances in moment-matching approximations, and the corresponding nonlinear driver/load interfaces. Future modeling, analysis, and design challenges will be considered throughout this paper.